1. Field of the Invention
The present invention relates to a semiconductor memory cell and semiconductor memory and, more particularly, to a dynamic memory cell requiring a refresh operation and a dynamic memory having an array of the memory cells.
2. Description of the Related Art
A one-transistor/one-capacitor type DRAM cell used in the conventional dynamic memory (DRAM) includes a charge transfer MOS transistor connected to a bit line and a word line, and a data storing capacitor connected to the MOS transistor. The DRAM cell itself does not have a refresh current supplying capability. It is necessary in the refresh operation that stored data are read onto the bit line side by turning on the charge transfer MOS transistor, and amplified by a sense amplifier and then rewritten into storage nodes from the bit line side. A refresh current is thus supplied.
When the DRAM cells are arranged in a matrix form to constitute a memory cell array, DRAM cells commonly connected to a bit line on the same column cannot be simultaneously refreshed if the refresh operation is effected on the bit line side by turning on the charge transfer transistor at the refreshing time as described above. At present, DRAM cells commonly connected to a word line on the same row are simultaneously refreshed. As a result, it becomes possible to simultaneously refresh only limited cells of a relatively small number determined by the word line unit in the memory cell array.